Designing a 16-Bit CPU from Logic Gates
A tour of a Logisim-Evolution CPU — program counter, accumulator, ALU and flags, stack, memory address register, step counter and a frame buffer.
- Published
- Nov 2026
- Reading
- 5 min
- Topics
- computer architecture, logisim, digital electronics
Why build one
Writing software on top of abstractions is easier when you've built the bottom layer once. This CPU was designed in Logisim-Evolution as a set of reusable sub-circuits, each small enough to reason about on its own.
The datapath
A program counter drives instruction fetch through the memory address register into the instruction register. Arithmetic runs through an accumulator and a B register into an ALU that supports ADD and SUB plus AND, OR, NOR, XOR and NOT. Separate X and Y registers hold coordinates for graphics output.
Flags and control flow
The flags register captures zero, carry, equal and less-than results, which drive conditional JUMP instructions. A hardware stack with STACK_UP and STACK_DOWN control lines makes calls and returns possible.
Control and I/O
A step counter sequences each instruction's micro-steps, asserting control lines such as RAM_WRITE, MAR_READ and STACK_WRITE at the right moment. A keyboard register, a TTY output and a frame buffer with an UPDATE_DISPLAY line let programs read input and draw to the screen. HALT stops the clock.
What it teaches
Every high-level construct reduces to a handful of control signals asserted on the right clock step. Debugging timing at this level makes pipeline hazards and race conditions in software feel much less abstract.